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Modeling a Programmable Logic Array

 

The programmable logic array is used to model a variety of logic devices. Each output consists of a gate which is chosen by the PLA type. The array is programmed by choosing which inputs are to be connected to each of the output gates. The programmable logic array may be used in conjunction with other logic gates to model commercial programmable logic devices such as the PAL series from National Semiconductor. This article will describe the process of modeling the PAL16C1 device from National's 20-Pin Small PAL Family.

The PAL16C1 device is a 20 pin device which has 16 dedicated inputs and one combinatorial pair of outputs. The other two pins are the power and ground pins. The PAL16C1 is created through National's Schottky TTL process. The internal logic of this device is available in National's Programmable Logic Devices data book. This device consists of three levels of logic: the logic array, one level of OR gates, and the combinatorial OR/NOR logic. The MC5 subcircuit listing of this device appears below.

*This subcircuit models the PAL16C1 from National Semiconductor
*
.subckt PAL16C1 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19
+ optional: 20=$G_DPWR 10=$G_DGND
+ params: MNTYMXDLY=0 IO_LEVEL=0
+ text: JEDEC_FILE=”PAL16C1.JED”

U1 PLANDC(16,16) 20 10
+ 2 1 3 19 4 18 5 17 6 14 7 13 8 12 9 11
+ ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10
+ ROW11 ROW12 ROW13 ROW14 ROW15 ROW16
+ DLY_16C1 IO_S MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
+ FILE=|JEDEC_FILE|

U2 ORA(8,2) 20 10
+ ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8
+ ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16
+ OR1 OR2
+ D0_GATE IO_S MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL

U3 OR(2) 20 10
+ OR1 OR2 16
+ D0_GATE IO_S MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}

U4 NOR(2) 20 10
+ OR1 OR2 15
+ D0_GATE IO_S MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}

.model DLY_16C1 upld (tplhTY=25ns tplhMX=35ns tphlTY=25ns tphlMX=35ns)

.ENDS

The subcircuit consists of the following sections.

The Subcircuit Header (.subckt)
The subcircuit header denotes the beginning of the subcircuit definition. It defines the node numbers that are used in calling the subcircuit, along with optional nodes and parameters. Although, the PAL16C1 is a 20 pin device, only 18 pins are listed in the subcircuit call. A check of the logic diagram will reveal that the missing pins, pins 10 and 20, are the ground and power pins. These two pins have been placed as optional pins through the "optional:" keyword. Their default values are the globally defined values of $G_DPWR and $G_DGND. Having the power and ground pins as optional pins lets you place the PAL16C1 on a schematic without having to externally connect it to power supplies. The two parameters, MNTYMXDLY and IO_LEVEL, control the digital delay and the digital I/O level, respectively, for the subcircuit. The default value of 0 specifies that these parameters will take the values of DIGMNTYMX and DIGIOLVL, which are set in the Global Settings. The keyword "text:" specifies a text parameter that lets you pass a text file to the subcircuit. The default file that the subcircuit will search for is "PAL16C1.JED". This text file is the one that will be used to program the programmable logic array.

The Programmable Logic Array (U1)
The programmable logic array is the core of the PAL16C1. As is shown in Figure 4, the array in the PAL16C1 consists of 16 pairs of true and complement inputs that feed 16 output AND gates. The appropriate <pld type> to use in this case is the PLANDC which is an AND array with true and complement inputs. The PLANDC is declared with 16 input pairs and 16 outputs. The optional nodes, 20 and 10, are tied to the power and ground pins of this device. The inputs are then declared, starting with the smallest input line number from Figure 4. The first input pin will be 2 since it is connected to the input line numbers 0 and 1. Then the other inputs are declared going from the next smallest input line number to the largest input line number. Each input will be connected to two consecutive input line numbers because the PLANDC is a complementary input array. After the inputs are defined, the 16 outputs are declared. These outputs can be given any name but will reference each row going from the smallest product line to the largest product line. In Figure 5, they are given the names ROW1 through ROW16. After the outputs appear the model names used by this device. DLY_16C1 is the <timing model name>. Since there is no feedback within the PAL16C1, all of the timing delay may be placed within this level of logic. The DLY_16C1 model statement appears at the bottom of the subcircuit in Figure 5. IO_S is the <I/O model name>. This model was chosen because the PAL16C1 was created through a Schottky TTL process. The model statement for IO_S is contained in the DIGIO.LIB file. The MNTYMXDLY, IO_LEVEL, and JEDEC_FILE parameters are all passed from the parameter declarations in the subcircuit heading.

The OR array (U2)
The OR array defines two 8 input OR gates. These gates are shown in Figure 4 with each having 8 of the programmable logic array outputs being fed into them (ROW1 through ROW16). The D0_GATE timing model name refers to a zero delay model that is stored in the DIGIO.LIB file.

The Combinatorial OR/NOR Logic (U3 and U4)
The U3 and U4 devices define a two input OR gate and a two input NOR gate. These two gates take the outputs of the OR array and produce the outputs at pins 15 and 16 of the PAL16C1 device.

Adding the PAL16C1 to the Component Menu
To access the PAL16C1 through the Component menu, the device must be linked to a shape and given pins in the Component Editor. To add a device, highlight the group that you would like to place it in, and then click on the Add Component command button. This places a new part into the highlighted group. The name should be the subcircuit name, but may actually be anything. The shape chosen was a 20 lead dip shape, and the device was defined as a subcircuit. The pins from the subcircuit header need to be entered in the Shape/pin display. We will leave out the optional pins because their default values suit our purposes. Click in the Shape/pin display, and type in the first pin "1". Place this at the first lead, and then repeat this process with the other 17 pins. Make sure that the pin names are defined as digital pins. The pin names must be the exact same names that they are defined as in the subcircuit header. Close and save the component settings. The device is now ready for placement in a schematic.

Using the PAL16C1 in a Schematic
The PAL16C1 may now be accessed through the Component menu. Select the device from the group that it was entered in and place it in the schematic. In the Attribute dialog box, a few of the attributes will have to be defined. The settings below show one way in which the PAL16C1 attributes may be defined. The PART attribute may be any name as long as it begins with an underscore or a letter. Having the PART attribute start with an X maintains SPICE compatibility. The NAME attribute must be the subcircuit name that was defined in the subcircuit header. The FILE attribute is the file name that the subcircuit is located in. This only needs to be defined if the file does not exist in the Nom.lib listing. The PARAMS attribute is left blank in order to use the values set in the Global Settings. The TEXT attribute passes a text parameter to the subcircuit. In this case, the text parameter will be the name of a JEDEC file that is used to program the PLA.

PART=X1
NAME=PAL16C1
FILE=PLA2.CKT
PARAMS:=
TEXT:=JEDEC_FILE="PLA2.JED"

A JEDEC file is an industry wide standard format for programming a PLD. It provides a table that indicates which fuses are to be programmed to implement the desired logic functions. Most, if not all, commercial PLD software should be able to create a JEDEC file. The JEDEC file, in this case, programs the PAL16C1 as an 8-bit equality comparator.

PLA test circuit
The test circuit was set up to compare two 8-bit stimulus generators. The figure below shows the results from this simulation. The HEX operator is used to transform the stimulus waveforms into hex values for an easier comparison. At 200ns and 700ns, the stimulus generators are generating the same output, and as a result, the PAL16C1 produces a logic 1 on its equality output, EQ. When the stimulus generators do not match, the NE, not equal, output is at an active high.

PLA simulation run
 
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